The present invention relates generally to logic circuits, and more particularly, to an incrementor/decrementor.
In many applications, conventional incrementor/decrementor circuits provide a simple function, namely increment by one or decrement by one. However, in some applications it is necessary to have the additional function of increment by two or decrement by two. Conventional logic circuits separate these two functions, but it would be desirable to have both functions in a single logic circuit.
Further, prior art incrementors propagate a carry chain in correspondence to the number of bits which are incremented. It would be desirable to reduce the propagation time for a carry chain in an incrementor circuit.